Generating Flat Flexible Soldered Cable Designs

The connection system (FFSC / Flat Flexible Soldered Cable?) described in my last post should allow for a high reliability, cost effective connection in medium to low density applications. To produce a similar design manually can be extremely time consuming due to the iterative nature of the problem.  If you need the design to be completely symmetrical then this process becomes harder. If you need to change something part way through, then really a piece of software to do it becomes essential.

The following Python script takes a set of parameters and generates an Eagle script to produce a FFSC design, including the top reinforcement layer. A basic example below:

ffsc-flat-flexible-soldered-connector-example-1

Almost all elements of the design can be adjusted to meet different applications, this includes all pad, track, spacing and reinforcement dimensions. Adjusting the length, taper and material thickness of the reinforcement layer allows you to get the mechanical gradient required for your application.

ffsc-flat-flexible-soldered-connector-example-2

For more involved applications, the script supports any number of segments to allow joining together of PCBs in non-parallel applications.

ffsc-flat-flexible-soldered-connector-example-3

The script is available to download from Github here.

Manufacturing

Whilst many design features of this connector type are new, the manufacturing processes required to make this connector are fairly standard. Most flex-capable PCB manufacturers should be able to produce this with a little thinking.

In volume, each layer is usually die cut out to the required shape before they are bonded together. In lower volumes or for prototyping purposes it may be possible to have each of these layers laser cut.

One thought on “Generating Flat Flexible Soldered Cable Designs”

  1. Hi Oliver,

    I tried to run the python code (downloaded and unchanged), but it keeps giving me “invalid syntax”, at line
    “def draw_wire_transform(segment_number, signal_name, layer_number, wire_width, (wire_start_x, wire_start_y), (wire_finish_x, wire_finish_y)):”

    If you can see this message, please help.

    Thanks very much!
    Dan

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